The present invention relates to the design and simulation of integrated circuit logic, and more particularly, but not exclusively, relates to the determination of derating factors to improve agreement between different integrated circuit design tools.
Computer-aided simulations and evaluations typically play a significant role in the development of a new integrated circuit design. As integrated circuit designs have become more complex, a complicated collection of design tools have arisen. Among these is the cell-level simulator that is used to gauge performance of individual logic cells made available by a given integrated circuit manufacturer. Typically, this type of simulator characterizes the behavior of the individual cells, such as basic combinational logic gates of the NAND, NOR, XOR, AND, OR, and INVERTER variety; more sophisticated combinational logic devices like multiplexors, counters, decoders, and encoders; and sequential logic devices like flip-flops and registers. Commonly, descriptions of these and other cells are provided by the manufacturer in the form of a computer readable library for Application Specific Integrated Circuit (ASIC) development using other higher level, design tools.
Among the higher level tools utilizing such cell libraries are logic synthesis programs that select and arrange the cells to provide the overall logic function of a desired integrated circuit design. Synthesis tools also typically interact with other tools that optimize circuit layout and analyze various circuit parameters to enhance development. Because of the complexity and sophistication of tools of this kind, a specialized industry of relatively few suppliers has arisen. Consequently, most ASIC manufacturers seek to provide a library of cell descriptions that is compatible with these higher level design tools.
Unfortunately, in striving to achieve compatibility, compromises are often made regarding certain library parameters. As a result, performance data provided by cell-level simulators may not always agree with higher level design tools. One particular area where disagreement may arise regards simulation under different operating conditions. Indeed, the techniques used by cell simulators to derate integrated circuit performance in terms of temperature, supply voltage, and process technology variation may be quite different from higher level tools. One reason for this difference is that application of cell-level derating techniques to all the cells in a given logic design may result in having to evaluate thousands of timing arcs. To reduce this computational burden, higher level tools sometimes utilize a set of derating factors to characterize all the cells in the library.
One common, higher level synthesis tool called “Design Compiler” is provided by Synopsys, Inc. of Mountain View, Calif. For this tool, derated performance is determined from a set of thirty different derating factors called “kfactors,” that are provided as part of the cell description library. The kfactors are grouped in three sets corresponding to process, voltage, and temperature. Each of the three sets has ten members corresponding to different types of timing arcs that are listed as follows: (1) propagation delay for a rising logic signal, (2) propagation delay for a falling logic signal, (3) transition delay for a rising logic signal, (4) transition delay for a falling logic signal, (5) setup time for a rising logic signal, (6) setup time for a falling logic signal, (7) hold time for a rising logic signal, (8) hold time for a falling logic signal, (9) minimum pulse width time for a high logic state, and (10) minimum pulse width time for a low logic state. The following kfactors numbered 1–10 individually designate each timing arc type for the process-based group:                1. k_process_rise_propagation        2. k_process_fall_propagation        3. k_process_rise_transition        4. k_process_fall_transition        5. k_process_setup_rise        6. k_process_setup_fall        7. k_process_hold_rise        8. k_process_hold_fall        9. k_process_min_pulse_width_high        10. k_process_min_pulse_width_lowThe following kfactors numbered 11–20 individually designate each timing arc type for the voltage-based group:        11. k_volt_rise_propagation        12. k_volt_fall_propagation        13. k_volt_rise_transition        14. k_volt_fall_transition        15. k_volt_setup_rise        16. k_volt_setup_fall        17. k_volt_hold_rise        18. k_volt_hold_fall        19. k_volt_min_pulse_width_high        20. k_volt_min_pulse_width_lowThe following kfactors numbered 21–30 individually designate each timing arc type for the temperature-based group:        21. k_temp_rise_propagation        22. k_temp_fall_propagation        23. k_temp_rise_transition        24. k_temp_fall_transition        25. k_temp_setup_rise        26. k_temp_setup_fall        27. k_temp_hold_rise        28. k_temp_hold_fall        29. k_temp_min_pulse_width_high        30. k_temp_min_pulse_width_low        
One prior art scheme used a cell-level simulator according to commonly owned U.S. Pat. No. 5,559,715 to Misheloff to determine kfactors for a cell library based on evaluation of propagation delay of only a single timing arc of only a single cell in the library. This prior art approach used the cell-level simulator to determine the propagation delay at the extremes of a temperature range and the extremes of a voltage range. The average of the propagation delays for the temperature extremes and the average of the propagation delays for the voltage extremes were calculated. The k_temp_rise_propagation kfactor was determined from the temperature extreme average and applied to all 10 of the different timing relationships within the temperature set (numbered 21–30), and the k_volt_rise_propagation kfactor was determined from the voltage extreme average and applied to all 10 of the different timing relationships in the voltage set (numbered 11–20), respectively. Further, with this technique, a value of 1 was used for all 10 kfactors relating to process technology (numbered 1–10), merely indicating the typical condition without deration. Consequently, only three different values were used for the 30 kfactors based on evaluation of only one timing arc type for only one cell in the library.
As the critical dimension of semiconductor transistors continues to decrease, sensitivity to derating conditions correspondingly increases. Thus, in order to reduce deration disparity between cell-level simulators and higher level simulation and evaluation tools, new techniques are needed to characterize derated performance.